1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication process therefor, and more particularly, to a semiconductor device forming an oxidation preventive film in a trench isolation structure therein and a fabrication process therefor.
2. Description of the Background Art
A stress is produced in the inner wall of a trench due to volume expansion of the inner wall of the trench, caused by oxidation in an oxidation process after formation of a trench isolation structure to thereby generate crystal defects such as dislocations and micro-defects in a silicon (Si) substrate. In order to prevent generation of the crystal defects, there has been available a technique forming an oxidation preventive film on the inner wall of the trench. Description will be given of a prior art technique forming the oxidation preventive film below.
FIGS. 18 to 24 are schematic sectional views showing a sequence of steps of a method of manufacturing a prior art semiconductor device. Referring to FIG. 18, for example, an insulating film 102 is formed on a p type silicon substrate 101.
Referring to FIG. 19, insulating film 102 is patterned by a photolithographic technique and an etching technique at the ordinary levels. By use of any convenient etching technique such as anisotropic dry etching with the patterned insulating film 102 as a mask, a trench 103 of a prescribed depth is formed on a surface of silicon substrate 101.
Referring to FIG. 20, in order to remove a damaged layer caused by the etching and furthermore, rounding the top edge portion of trench 103, a silicon oxide layer 104 is formed on the inner wall of trench 103.
Referring to FIG. 21, in order to prevent oxidation of the inner wall of trench 103 in a subsequent oxidation step, an oxidation preventive film 106 is formed. Oxidation preventive film 106 is formed as a silicon nitride film at the interface between silicon substrate 101 and silicon oxide film 104 by annealing silicon substrate 101 in an atmosphere including nitrogen (N).
Referring to FIG. 22, a filling oxide film 107 constituted of a silicon oxide film is formed on insulating film 102 so as to fill trench 103. Thereafter, by annealing silicon substrate 101 at a prescribed temperature in a prescribed atmosphere, filling oxide film 107 is densified. Thereafter, the surface of silicon substrate 101 is planarized by means of a CMP (Chemical Mechanical Polishing) method and subsequently, insulating film 102 on an active region is removed by wet etching.
Referring to FIG. 23, the CMP and the wet etching exposes the surface of silicon substrate 101 while leaving filling oxide film 107 so as to fill trench 103, thus completing a trench isolation structure.
Referring to FIG. 24, a gate oxide film 108 is formed on the surface of silicon substrate 101 by oxidation. The oxidation is effected by introducing hydrogen gas and oxygen gas into a reaction vessel accommodating wafers after the gases react with each other, or introducing only oxygen gas into the reaction vessel. Thereafter, a gate electrode is formed on gate oxide film 108 and subsequent to this, an impurity is ion implanted into silicon substrate 101 with the gate electrode or the like as a mask, thereby forming a pair of source/drain regions on the surface of silicon substrate 101. In such a way, there are formed a MOS (Metal Oxide Semiconductor) transistor used in DRAM (Dynamic Random Access Memory) and others, and a floating-gate transistor used in EEPROM (Electrically Erasable Programmable Read Only Memory) and others.
In the above semiconductor device, oxidation preventive film 106 is formed on the inner wall of a trench isolation structure. Therefore, a film thickness of gate oxide film 108 shows thinning as depicted in FIG. 25 at the top edge portion of the trench isolation structure (on the oxidation preventive film 106). That is, a film thickness TA3 of gate oxide film 108 at the top edge portion of the trench isolation structure is thinner than those of the other parts, having resulted in a problem of difficulty in forming a high reliability gate oxide film 108.